1. Field of the Invention
Generally, the present disclosure relates to integrated circuits and methods for the formation thereof, and, more particularly, to integrated circuits including field effect transistors other than core device transistors and/or transistors that can be operated at a higher voltage than core device transistors.
2. Description of the Related Art
Integrated circuits include a large number of circuit elements which include, in particular, field effect transistors. In a field effect transistor, a gate electrode is provided that may be separated from a channel region by a gate insulation layer providing an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region may be formed which are doped differently than the channel region.
Integrated circuits including field effect transistors may be formed in accordance with semiconductor-on-insulator (SOI) technology, wherein the source, channel and drain regions of the transistors are formed in a relatively thin semiconductor layer that is separated from a support substrate, which may be a semiconductor substrate, for example a silicon wafer or die, by an electrically insulating layer, which may be a silicon dioxide layer. SOI technology may have some advantages associated therewith which include a reduced power consumption of an SOI integrated circuit compared to a bulk semiconductor integrated circuit having the same performance. Moreover, in some examples of SOI technology, which are denoted as fully depleted semiconductor-on-insulator (FDSOI) technology, a thickness of the semiconductor layer wherein the source, channel and drain regions of the transistors are formed may be adapted such that a full depletion of the channel region of the transistors may be obtained in the operation of the transistors. Thus, the electrostatic control of the channel regions of the transistors may be improved, effects of random dopant fluctuations may be reduced, and leakage currents of the transistors may be reduced.
SOI technology may allow for doped back gate regions in the support substrate below the electrically insulating layer that separates the support substrate from the semiconductor material of the source, channel and drain regions of the transistors. The type of doping and the dopant concentration in a back gate region provided below a transistor may have an influence on the threshold voltage of the transistor that needs to be applied to the gate electrode of the transistor for switching the transistor between an OFF-state, wherein the transistor has only a small electrical conductivity, and an ON-state, wherein the transistor has a relatively high electrical conductivity. Additionally, the threshold voltage of the transistor may be influenced by applying a bias voltage to the back gate region.
The threshold voltage of a field effect transistor may be related to a leakage current that flows through the transistor in the OFF-state. Typically, a lower threshold voltage is associated with an increased leakage current and vice versa. Lowering the threshold voltage of the field effect transistors in an integrated circuit may help to increase the speed of operation of logic gates wherein the transistors are provided, whereas a reduction of the leakage current may help to reduce power consumption.
In advanced technology nodes such as, for example, the 22 nm technology node and below, fully depleted semiconductor-on-insulator technology may be used in combination with doped back gate regions. Thus, different variants of core device transistors including super-low threshold voltage (SLVT) core device transistors, low threshold voltage (LVT) core device transistors, regular threshold voltage (RVT) core device transistors and high threshold voltage (HVT) core device transistors may be provided. Each of these variants of core device transistors may be provided both for P-channel transistors and N-channel transistors. Furthermore, different variants of input/output transistors, which may include super-low threshold voltage input/output transistors and low threshold voltage input/output transistors, may be provided.
For some applications, it may be desirable to provide types of field effect transistors other than core device transistors and input/output transistors in integrated circuits wherein fully depleted semiconductor-on-insulator technology is employed. Such other types of field effect transistors may include transistors that are adapted for operation at a relatively high voltage of about 10 V or more between their gate electrodes and their source/drain electrodes. Further types of field effect transistors that may be desirable for some applications include depletion transistors, which are in their ON-state when mass potential is applied at their gate electrodes, as opposed to enhancement transistors, which are in their OFF-state when mass potential is applied at their gate electrodes. Depletion transistors may be used in automotive applications and in length regulators at charge pumps. Charge pumps may be provided in fully depleted semiconductor-on-insulator integrated circuits to generate the back gate voltages for the logic circuit parts.
In view of the above considerations, the present disclosure provides techniques that may allow the formation of depletion transistors and transistors that may be operated at relatively high voltages in an integrated circuit wherein fully depleted semiconductor-on-insulator technology is employed. In particular, in some embodiments, the present disclosure can provide techniques for the formation of such transistors wherein processes and mask layers that are also used for the formation of other devices in a fully depleted semiconductor-on-insulator integrated circuit may be employed for the formation of depletion transistors and/or higher voltage transistors.